1. Technology Field
The present invention generally relates to a flash memory unit, in particular, to a NAND flash memory unit as well as an operating method and a reading method of the memory unit.
2. Description of Related Art
A NAND structure has been widely used in the design of non-volatile memory devices to increase storage density. A NAND flash memory unit commonly includes a plurality of memory cells concatenating to each other. Along with process shrink, there exist many difficulties in manufacturing NAND flash memory units that may lead to decreases in data reliability. In recent years, many three-dimensional NAND flash memory units such as a terabit cell array transistor (TCAT), a stacked memory array transistor (SMArt) or a bit coast scalable (BiSC) technology are proposed in the industry to alleviate the problems during the process shrink. Silicon nitride is used for storing data in some of the three-dimensional NAND flash memory units, and yet there exists a trade-off between the data retention and the erasing speed in such memory cells. Once the erasing speed is increased, the data retention may be worse. Accordingly, to maintain the erasing speed and the data retention of such memory cells is highly concerned by those skilled in the art.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.